This invention relates generally to a differential emitter-coupled logic buffer having reduced power dissipation, and more particularly to a logic buffer having a differential emitter-coupled pull-down circuit which increases the discharge rate of differential outputs of the logic buffer.
Emitter-coupled logic (ECL) buffers use resistor-loaded, common-emitter differential pairs to realize combinatorial functions such as NOR and NAND. Emitter-follower buffer circuits are appended to the outputs of the differential pairs to perform level shifting and to allow the gate to drive large capacitive loads without drastically increasing the gate delay and output rise and fall times. ECL buffers inherently produce both true and complement outputs. Often, a pair of emitter followers is used to transmit the differential signals to preserve signal fidelity while transmitting the output of the buffer to a remote receiver.
However, prior art emitter-follower buffers which drive large capacitive loads typically suffer from asymmetrical rising and failing edges of the output signals. In the typical case of an NPN emitter follower, the output rising edge can be very fast since the drive current from the pull-up circuit, which operates common collector, increases substantially (limited only by its base current), whereas during the output falling edge, the pull-up circuit turns off and the edge rate is limited by the fixed drive current of the pull-down circuit, which is typically a current source or resistor.
The asymmetric output rise and fall times have the additional undesirable effect of causing the propagation delay to depend on whether the data is rising or falling. To speed up the falling edge, the quiescent current in the pull-down circuit must be increased at the expense of power dissipation. This current is wasted during the rising transition. In a typical ECL buffer having an emitter follower which must drive a heavy capacitive load, the power dissipation and gate delay are dominated by the output buffer rather than the logic gate function. A differential ECL gate suffers doubly since it has two emitter followers.
One example of a prior art ECL buffer includes a differential device having differential inputs and corresponding differential outputs. Each differential output is coupled to a voltage source through a pull-up transistor and to a reference voltage through a current source. The base of each of the pull-up transistors is connected to an output node of the differential device for controlling the operation of the pull-up transistor. When a logic high is present at the base of the pull-up transistor, the pull-up transistor is turned on and the associated output terminal is charged. When the voltage at the base of the pull-up transistor is at a logic low, the transistor is turned off and the output terminal is discharged through the current source. However, because the current source is always on, it is always dissipating power regardless of whether or not the output terminal is being discharged. In other words, even when the output terminal is being charged through the pull-up transistor, the current source is dissipating power. Furthermore, due to the fixed current generated by the current source, the output terminal is discharged at a slower rate than the rate at which it is charged by the pull-up transistor. An increase in the amplitude of the current source in order hasten the discharge times results in additional power dissipation when the output terminal is not being discharged.
Another prior art ECL gate includes a PNP transistor in the place of the current source of the gate described above for discharging the output terminal. However, while this gate reduces power dissipation by not using a current source for discharging the output terminal, the overall circuit requires additional transistors for proper operation of the PNP transistor, and PNP transistors, by their nature, are much slower than similarly sized NPN transistors.
Yet another prior art ECL gate includes a pull-down device having a number of NPN transistors and capacitors which must be properly tuned to increase the symmetry between the rising and falling edges of the voltage at the output terminal. However, this prior art device requires a large area to implement the capacitors and an increased number of transistors and, due to the tuning required for the circuit to operate properly, the circuit is much more complex to maintain in proper operating condition.
It is therefore an object of this invention to provide an emitter-coupled logic buffer having reduced power dissipation.
It is a further object of this invention to provide such an emitter-coupled logic buffer with reduced output load discharge times.
It is a further object of this invention to provide an emitter-coupled logic buffer having symmetrical rising and falling edges of the output voltage.
It is a further object of this invention to provide such an emitter-coupled logic buffer which eliminates the need for fast complementary devices such as PNP transistors.
It is a further object of this invention to provide such an emitter-coupled logic buffer having a reduced number of transistors.
The invention results from the realization that a low-power, symmetrical emitter-coupled logic buffer can be achieved by using an emitter-coupled pair of transistors as a differential pull-down circuit for alternately discharging output loads through a common discharge path.
This invention features a logic buffer including a logic gate having at least two input terminals and two output nodes, a plurality of output terminals, each having a capacitance associated therewith and a pull-up circuit interconnected between each output node and the plurality of output terminals for alternately charging the capacitance of each output terminal. The buffer also includes a differential pull-down circuit including a pull-down current source, the pull-down circuit interconnected between the output nodes and the output terminals for inversely alternately discharging the capacitances through the pull-down current source for accelerating the discharge of the capacitance of the respective output terminal.
In a preferred embodiment, the differential pull-down circuit may include a plurality of emitter-coupled transistors, each being electrically connected to one of the plurality of output terminals, the emitters of each of the transistors being electrically connected to the common pull-down current source. The buffer may include first and second output terminals and the logic gate may include a differential device having first and second differential input terminals and first and second differential output nodes. The pull-up circuit may include a first transistor electrically connected between the first output node and the first output terminal for charging the capacitance of the first output terminal, and a second transistor electrically connected between the second output node and the second output terminal, for charging the capacitance of the second output terminal. The differential pull-down circuit may include third and fourth emitter-coupled transistors, the third transistor being electrically connected to the first output terminal for discharging the capacitance of the first output terminal, and the fourth transistor being electrically connected to the second output terminal for discharging the capacitance of the second output terminal, the emitters of the third and fourth transistors being electrically connected to a reference voltage source through the common pull-down current source. The differential pull-down circuit may further include a fifth transistor electrically connected between the first output node and the fourth transistor, for controlling the state of the fourth transistor, and a sixth transistor electrically connected between the second output node and the third transistor, for controlling the state of the third transistor. The differential pull-down circuit may further include a first diode electrically connected between the fourth and fifth transistors and a second diode electrically connected between the third and sixth transistors. A base terminal of the first transistor may be electrically connected to an emitter terminal of the fifth transistor, a base terminal of the second transistor may be electrically connected to an emitter terminal of the sixth transistor and the common current source may be a fixed current source. The differential pull-down circuit may include a plurality of semiconductor switches, each having a control terminal, a first terminal and a second terminal, each of the semiconductor switches being electrically connected to one of the plurality of output terminals, the second terminals of each of the semiconductor switches being electrically connected to the common pull-down current source. The pull-up circuit may include a first semiconductor switch electrically connected between the first output node and the first output terminal for charging the capacitance of the first output terminal and a second semiconductor switch electrically connected between the second output node and the second output terminal, for charging the capacitance of the second output terminal. The differential pull-down circuit may include third and fourth semiconductor switches each having first and second terminals, the third transistor having its first terminal electrically connected to the first output terminal for discharging the capacitances of the first output terminal. The fourth transistor may have its first terminal electrically connected to the second output terminal for discharging the capacitance of the second output terminal, and the second terminal of the third and fourth transistors may be electrically connected together and to a reference voltage source through the common pull-down current source. The differential pull-down circuit may further include a fifth semiconductor switch electrically connected between the first output node and the fourth semiconductor switch, for controlling the state of the fourth semiconductor switch and a sixth semiconductor switch electrically connected between the second output node and the third semiconductor switch, for controlling the state of the third semiconductor switch. The differential pull-down circuit may further include a first diode electrically connected between the fourth and fifth semiconductor switches and a second diode electrically connected between the third and sixth semiconductor switches. A control terminal of the first semiconductor switch may be electrically connected to a terminal of the fifth semiconductor switch and a control terminal of the second semiconductor switch may be electrically connected to a terminal of the sixth semiconductor switch. Each of the capacitances may be associated with a load coupled to each of the plurality of output terminals or associated with parasitic loads at each of the plurality of output terminals.
This invention also features a logic buffer including a logic gate having at least two input terminals and two output nodes, a plurality of output terminals, each having a capacitance associated therewith and a pull-up circuit electrically connected between each of the output nodes and the plurality of output terminals for selectively charging the capacitance of each output terminal. A pull-down circuit is electrically connected between each of the output nodes and the plurality of output terminals for selectively discharging the capacitances of each of the output terminals through a single discharge path. The pull-up circuit and the pull-down circuit cooperate to alternately charge and discharge the capacitances of each of the output terminals.
In a preferred embodiment, the pull-down circuit may include a plurality of emitter-coupled transistors, each transistor being electrically connected to one of the plurality of output terminals, the emitters of each of the transistors being electrically connected to the single discharge path. The single discharge path may include a fixed current source. The buffer may include first and second output terminals and the logic gate may include a differential device having first and second differential input terminals and first and second differential output nodes. The pull-up circuit may include a first transistor electrically connected between the first output node and the first output terminal for charging the capacitance of the first output terminal, and a second transistor electrically connected between the second output node and the second output terminal, for charging the capacitance of the second output terminal. The differential pull-down circuit may include third and fourth emitter-coupled transistors, the third transistor being electrically connected to the first output terminal for discharging the capacitance of the first output terminal, and the fourth transistor being electrically connected to the second output terminal for discharging the capacitance of the second output terminal, the emitters of the third and fourth transistors being electrically connected to a reference voltage source through the common pull-down current source. The differential pull-down circuit may further include a fifth transistor electrically connected between the first output node and the fourth transistor, for controlling the state of the fourth transistor, and a sixth transistor electrically connected between the second output node and the third transistor, for controlling the state of the third transistor. The differential pull-down circuit may further include a first diode electrically connected between the fourth and fifth transistors and a second diode electrically connected between the third and sixth transistors. A base terminal of the first transistor may be electrically connected to an emitter terminal of the fifth transistor, a base terminal of the second transistor may be electrically connected to an emitter terminal of the sixth transistor and the common current source may be a fixed current source.